The implementation of a Turbo Codec in a PLD

In order to move their businesses forward, in a competitive way, the manufa cturers of field programmable devices such as CPLDs/FPGAs must embrace new disciplines and skills. In this paper, authors from one company, Altera, re views and discusses one the most advanced forward error correction (FEC) te chniques, 'Turbo Coding' that, alongside other error correction techniques, is available as IP for implementation in its field programmable devices. A s well as reviewing the operation of a Turbo Codec, its implementation in a PLD is also covered.