Adiabatic dynamic CMOS logic circuit

In this study, an adiabatic dynamic CMOS logic (ADCL) circuit for superlow power consumption is proposed and the effectiveness of the circuit is prove n by circuit analysis, computer simulation, and experiments using discrete devices. The mutual interconnect between the logic circuits is as easy as t hat of CMOS circuits and the power consumption of the logic circuit is two orders of magnitude lower than that of a CMOS circuit. When the inverter ci rcuit with FETs with W/L = 10 mu/1.5 mu and a load capacitance of 0.1 pF is operated using a triangle wave with a clock frequency of 1 MHz and amplitu de of 5 V, the power consumption is 0.39 pJ. On the other hand, in a CMOS i nverter operated under the above conditions, the power consumption is 23 pJ . (C) 2000 Scripta Technica.