Phase-locked loop design for on-chip tuning applications

Authors
Osa, JI Carlosena, A Lopez-Martin, AJ
Citation
Ji. Osa et al., Phase-locked loop design for on-chip tuning applications, ELECTR LETT, 36(8), 2000, pp. 699-701
Citations number
6
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
36
Issue
8
Year of publication
2000
Pages
699 - 701
Database
ISI
SICI code
0013-5194(20000413)36:8<699:PLDFOT>2.0.ZU;2-W
Abstract
A novel phase-locked loop scheme is proposed, the main application of which is in on-chip tuning circuits. It involves the use of a variable gain ampl ifier and also a frequency tunable loop filter, providing infinite hold-in range, a fractionally constant pull-out range and also a fractionally const ant ripple.