A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation

The continuous improvement in the performance and the increases in the size s of VLSI systems make electrical interconnect and package (EIP) design and modeling increasingly more important. Special software tools must be used for the design of high-performance VLSI systems. Furthermore, larger and fa ster systems require larger and more accurate circuit models. The partial e lement equivalent circuit (PEEC) technique is used for modeling such system s with three-dimensional full wave models. In this paper, we present a prac tical, readily parallelizable procedure for generating reduced-order freque ncy-domain models from general full wave PEEC systems, We use multiple expa nsion points, and piecemeal construction of pole-residue approximations to transfer functions of the PEEC systems, as was used in the complex frequenc y hopping algorithms. We consider general, multiple-input/multiple-output P EEC systems, Our block procedure consists of an outer loop of local approxi mations to the PEEC system, coupled with an inner loop where an iterative m odel-reduction method is applied to the local approximations. We systematic ally divide the complex frequency region of interest into small regions and construct local approximations to the PEEC system in each subregion. The l ocal approximations are constructed so that the matrix factorizations assoc iated with each of them are the size of the original system and independent of the order of the approximation. Results of computations on these local systems are combined to obtain a reduced-order model for the original PEEC system. We demonstrate the usefulness of our approach with three interestin g examples.