A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver

As integrated circuit (IC) manufacturing technology pushes toward the deep submicron (DSM) regime, the interconnect behavior begins to dominate the ov erall chip performance, Traditional interconnect characterization methods d o not offer the required accuracy or the versatility to tackle challenges o f DSM design. We present a system for interconnect parasitic capacitance ex traction using an extremely fast three-dimensional (3-D) solver, capable of handling general geometry configurations and providing high accuracy, The contributions in this work make 3-D field solvers an attractive and, for th e first time, computationally feasible approach to calculating interconnect parasitics. The system represents a significant performance leap in 3-D in terconnect characterization, making it well suited for full-chip extraction and for high-accuracy characterization of critical nets, block IF, and sta ndard and custom cell designs.