Performance optimization by interacting netlist transformations and placement

Performance optimization has become one of the most important problems at a ll design stages of today's highly integrated circuits. During logic synthe sis performance optimization is guided by only rough net delay models. Ther efore, net delays cannot be optimized effectively during Logic synthesis. A s device dimensions are shrinking in deep submicron designs, net delays ten d to dominate performance. Consequently, the netlist generated during logic synthesis is suboptimal as only rough approximations for the most dominant part of the path delays are available. In this paper, we present a placeme nt approach that exploits the optimization potential of netlist transformat ions during placement. As netlist transformations are integrated into the p lacement process, they can be guided by more accurate net delay models. In contrast to previous approaches that apply netlist transformations during p lacement, our approach is not restricted to local transformations like buff er insertion and gate resizing, but exploits global dependencies between th e signals in a circuit. On the average, the maximum path delay is reduced b y 11% compared to the initial performance-driven placement of the original netlist, Furthermore, the experiments show that applying the same netlist t ransformation procedure before placement yields no improvement as net delay s cannot be considered due to missing layout information.