Prior reported PSPICE modeling work has demonstrated subnanosecond field ri
se-times for a head driven by an ideal current source. Results including th
e flexure interconnection have demonstrated 1 ns field rise-times without p
ulse distortion. Three write driver designs are explored. A simple H-bridge
, an H-bridge with fly-over diodes, and an H-bridge with clamped transistor
s to improve switching speed are compared. The driver models are implemente
d using BJTs with state-of-the-art industry MOSIS process model parameters
for PSPICE. The simulations show that for the low inductances considered an
d the relatively high supply voltage employed, the fly-over diodes are not
required. The H-bridge with clamped transistors is the fastest driver (50 O
mega resistive load) but suffers from a limited current capability for the
small transistor areas required for high speed. The driver designs are rest
ricted by termination requirements which generally do not correspond to opt
imum switching times for the 50 Omega resistive load used for preliminary e
valuation. Finally, by reducing the interconnection length to 25 mm, stacki
ng the head turns, and using the simple H-bridge driver, it is demonstrated
that a field rise-time of less than 0.2 ns can be achieved. The resulting
waveform is presented and the implications discussed. (C) 2000 American Ins
titute of Physics. [S0021-8979(00)58608-3].