The efficient charge recovery logic (ECRL) is reported as a promising candi
date for low-power applications. However, in the design of digital systems,
essential building blocks such as the flip-flops cannot be neglected. In t
his paper, adiabatic switching or energy recovery technique is used in the
design of low-power flip-flops. In particular, SR and JK flip-flop designs
based on the ECRL architecture are proposed. From the HSPICE simulation res
ults, these adiabatic Rip-flops have shown significant improvement in terms
of power consumption over their CMOS counterparts. In addition, the design
of an adiabatic sequential circuit is illustrated using the example of a 4
-bit binary counter. (C) 2000 Elsevier Science Ltd. All rights reserved.