POWER OPTIMIZATION IN VLSI LAYOUT - A SURVEY

Authors
PEDRAM M VAISHNAV H
Citation
M. Pedram et H. Vaishnav, POWER OPTIMIZATION IN VLSI LAYOUT - A SURVEY, Journal of VLSI signal processing systems for signal, image, and video technology, 15(3), 1997, pp. 221-232
Citations number
56
Categorie Soggetti
Computer Sciences, Special Topics","Engineering, Eletrical & Electronic","Computer Science Information Systems
Journal title
Journal of VLSI signal processing systems for signal, image, and video technology → ACNP
ISSN journal
13875485
Volume
15
Issue
3
Year of publication
1997
Pages
221 - 232
Database
ISI
SICI code
1387-5485(1997)15:3<221:POIVL->2.0.ZU;2-D
Abstract
This paper presents a survey of layout techniques for designing low po wer digital CMOS circuits. It describes the many issues facing designe rs at the physical level of design abstraction and reviews some of the techniques and tools that have been proposed to overcome these diffic ulties.