AN ALGORITHM ADAPTED AUTONOMOUS CONTROLLING CONCEPT FOR A PARALLEL SINGLE-CHIP DIGITAL SIGNAL PROCESSOR

Recent sub-mu semiconductor technology supports the monolithic integra tion of multiprocessor systems. High wiring density and short on-chip memory access cycles motivate novel architecture concepts, outperformi ng conventional parallel systems. An efficient controlling strategy is a key to gain high performance from limited silicon resources. In thi s paper, a controlling concept for a monolithic Autonomous Single-Inst ruction/Multiple Data (ASIMD) processor is presented, which combines t he high parallelism of an SIMD approach with the flexibility of standa rd DSP architectures. To demonstrate the performance gains of the conc ept, a digital video signal processor, the HiPAR-DSP has been implemen ted. It consists of an array of 4 or 16 datapaths, local memories for each datapath, a shared memory with concurrent data access in shape of a matrix and a central RISC controller. A three stage execution auton omy has been implemented, consisting of conditional instructions, cond itional skip of instructions by the data paths and global evaluation o f local conditions by the central controller. This allows efficient ex ecution of data dependent medium- and high-level algorithms with very low controlling overhead. A performance of up to two arithmetic gigaop erations per second is achieved for algorithms with irregular data flo w or control flow for the 100 MHz clocked processor with 16 data paths .