Reducing test application time by scan flip-flops sharing

The test application time is reduced while preserving the test quality or t he fault coverage for circuit testing. The goal is achieved by reducing the number of scan flip-flops required for a scan-based design, and the basic procedure is to look for groups of "s-independent inputs." The s-independen t inputs in a group have the property that, when these inputs an combined t ogether to share a scan flip-flop, the originally detectable faults are sti ll detectable under the new scan structure. Though the number of test vecto rs may slightly increase, this can be offset by the significant reduction i n the scan test width. Thus, the goal of test time reduction for scan test can be accomplished. For circuits which have few s-independent inputs, bypa ss storage cells are added to increase the s-independencies among all input s. Experiments have been performed on MCNC benchmarks and the results are g ood. Several benchmark circuits have shown more than 90% of test time reduc tion.