An automatic generator is developed which can synthesise fixed-point multip
liers of any bit accuracy with a speed performance comparable to other rece
ntly proposed full-custom results. This synthesiser performs global optimis
ation for the interconnection of compression elements to minimise the delay
in the partial product summation tree (PPST). Also, the final adder follow
ing the PPST is carefully synthesised to reduce the cost without sacrificin
g the speed performance. Unlike the full-custom design method, our synthesi
ser is adaptable to any technology change. A significant improvement is ach
ieved compared to the Synopsys synthesis results.