A 16-bit 250-kHz delta-sigma modulator and decimation filter

Authors
Maulik, PC Chadha, MS Lee, WL Crawley, PJ
Citation
Pc. Maulik et al., A 16-bit 250-kHz delta-sigma modulator and decimation filter, IEEE J SOLI, 35(4), 2000, pp. 458-467
Citations number
19
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
35
Issue
4
Year of publication
2000
Pages
458 - 467
Database
ISI
SICI code
0018-9200(200004)35:4<458:A12DMA>2.0.ZU;2-V
Abstract
This paper describes a delta-sigma analog-to-digital converter (ADC) capabl e of converting input frequencies up to 250 kHz. It consists of a fifth-ord er switched-capacitor delta-sigma modulator and a decimation filter. Variou s design optimizations in the modulator are presented. The decimation filte r consists of a comb filter followed by a novel, highly efficient and scala ble finite impulse response filter, The ADC was implemented in 0.6-mu m CMO S technology. It achieves a dynamic range of 94 dB.