Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of550 ps acid an operating frequency of 900 MHz

This paper describes power reduction circuit techniques in an ultra-high-sp eed emitter-coupled Logic (ECL)-CMOS SRAM, Introduction of a 0.25-mu m MOS transistor allows a Y decoder and a bit-line driver to be composed of CMOS circuits, resulting in a power reduction of 33%. Moreover, a variable-imped ance load has been proposed to reduce cycle time. A I-Mb ECL-CMOS SRAM was developed by using these circuit techniques and 0.2-mu m BiCMOS technology. The fabricated SRAM has an ultrafast access time of 550 ps and a high oper ating Frequency of 900 MHz with a power dissipation of 43 W.