A 1-V, 8-bit successive approximation ADC in standard CMOS process

A 1-V 8-bit 50-kS/s successive approximation analog-to-digital converter (A DC) implemented in a conventional 1.2-mu m CMOS process is presented. Low v oltage, large signal swing sample-and-hold, and digital-to-analog conversio n are realized based on inverting op-amp configurations with biasing curren ts added to the op-amp negative input terminal so that the op-amp input com mon-mode voltages can be biased near ground to minimize the supply voltage. At the same time, the input and output quiescent voltages can be set at ha lf of the supply rails. Low-voltage latched comparator is realized based on current-mode approach. The entire ADC including all the digital circuits c onsumes Less than 0.34 mW. An effective number of bits of 7.9 was obtained for a 1-kHz 850-mV peak-to-peak input signal.