Return-limited inductances: A practical approach to on-chip inductance extraction

Decreasing slew rates and efforts to reduce the resistance-capacitance (RC) delays of on-chip interconnect through design and technology have resulted in the growing importance of inductance in analyzing interconnect response for timing and noise analysis. In this paper, we consider a practical appr oach for extracting approximate inductances of on-chip interconnect. This a pproach, which,ve call the method of return-limited inductances, is based o n performing the inductance modeling of signal lines and power-ground lines independently and on taking advantage of the power and ground distribution of the chip to localize inductive coupling. A set of simple geometry-based matrix decomposition rules guide sparsification in these extractions.