A dedicated DSP architecture for discrete wavelet transform

This paper presents the architecture of a DSP dedicated to discrete wavelet transform. The architecture consists in 2 microprogrammable processors who se complementarity enables to avoid any wait cycles during the algorithm ex ecution so that the available computation power is continuously used. Thank s to this bi-processor organization, a 160000-transistor ASIC coupled to a small external SRAM implements in real time a 3-stage multiresolution trans form on a CCIR 601 video signal. This chip has been realized in a 0.7 mu m double metal CMOS technology. Moreover, the DSP has a full programmability with respect to the used filters and the picture format; it also has the po ssibility to take into account edge effects and therefore improve image qua lity. The circuit can be used in the coding as well as in the decoding.