Design of 25-nm SALVO PMOS devices

Citation
Hh. Vuong et al., Design of 25-nm SALVO PMOS devices, IEEE ELEC D, 21(5), 2000, pp. 248-250
Citations number
8
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE ELECTRON DEVICE LETTERS
ISSN journal
07413106 → ACNP
Volume
21
Issue
5
Year of publication
2000
Pages
248 - 250
Database
ISI
SICI code
0741-3106(200005)21:5<248:DO2SPD>2.0.ZU;2-V
Abstract
The concept and preliminary designs of novel self-aligned local-channel V-g ate by optical lithography (SALVO) devices are presented. SALVO uses optimi zed local-channel doping to sharpen the lateral junctions, in order to mini mize short channel effect for gate lengths down to 25 nm. In addition, it u tilizes the replacement-gate design with inner spacers to Facilitate integr ation of alternative gate stack materials and to extend the application of optical lithography. SALVO PMOS designs with both metal gate and poly-metal gate electrodes were studied, the latter proving capable of delivering hig h performance 25 nm PMOS with currently manufacturable professes.