A source-line programming scheme for low-voltage operation NAND flash memories

To realize a low-voltage operation NAND flash memory, a new source-line pro gramming scheme has been proposed, This architecture drastically reduces th e program disturbance without circuit area, manufacturing cost, program spe ed, or power consumption overhead. In order to improve the program disturba nce characteristics, a high program inhibit voltage is applied to the chann el from the source line, as opposed to from the bit line of the conventiona l scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption, Although the conventional NAND flash memory cannot operate be low 2.0 V due to the program disturbance issue, the proposed NAND flash mem ory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 mu s/page and a very low po wer operation of 22 mW at 1.4 V can be realized in the proposed scheme.