A novel dateline redundancy suitable for an embedded DRAM macro with wide d
ata bus is presented. This redundancy reduces the area required for spare c
ells from 6 to 1.6% of the area required for normal cells and improves chip
yield from 50 to 80%. In addition, it provides a high speed data path. An
embedded DRAM macro adopting the redundancy achieves 200-MHz operation and
provides 51.2-Gbit/s bandwidth. It has been fabricated with 0.25-mu m techn
ology.