A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's

Authors
Hoenigschmid, H Frey, A DeBrosse, JK Kirihata, T Mueller, G Storaska, DW Daniel, G Frankowsky, G Guay, KP Hanson, DR Hsu, LLC Ji, B Netis, DG Panaroni, S Radens, C Reith, AM Terletzki, H Weinfurtner, O Alsmeier, J Weber, W Wordeman, MR
Citation
H. Hoenigschmid et al., A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's, IEEE J SOLI, 35(5), 2000, pp. 713-718
Citations number
6
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
35
Issue
5
Year of publication
2000
Pages
713 - 718
Database
ISI
SICI code
0018-9200(200005)35:5<713:A7CABA>2.0.ZU;2-X
Abstract
A 7F(2) DRAM trench cell and corresponding vertically folded bitline (BL) a rchitecture has been fabricated using a 0.175 mu m technology. This concept features an advanced 30 degrees tilted array device layout and an area pen alty-free inter-BL twist, The presented scheme minimizes local well noise b y maximizing the number of twisting intervals. A significant improvement of signal margin was measured on a 32-Mbyte test chip.