A 3.6-Gb/s 340-mW 16 : 1 pipe-lined multiplexer using 0.18 mu m SOI-CMOS technology

This paper describes a 16:1 multiplexer using 0.18 mu m SOI-CMOS technology . To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architectur e, This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices, The multiplexer achieves 3.6 Gbls at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.