High performance damascene metal gate MOSFET's for 0.1 mu m regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In th is process, the gate insulators and gate electrodes are formed after ion im plantation and high temperature annealing (similar to 1000 degrees C) for s ource/drain formation, and the gate electrodes are fabricated by chemical m echanical polishing (CMP) of gate materials deposited in grooves. Metal gat es and high dielectric constant gate insulators are applicable to the MOSFE T, since the processing temperature after gate formation can he reduced to as Low as 450 degrees C. Furthermore, process-damages on gate insulators ar e minimized because there is Do plasma damage caused by source/drain ion im plantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transi stors with SiO2 or Ta2O5 as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low ga te sheet resistivity no gate depletion and drastic improvement in gate oxid e integrity, resulting in high transistor performance.