Aw. Wang et Kc. Saraswat, A strategy for modeling of variations due to grain size in polycrystallinethin-film transistors, IEEE DEVICE, 47(5), 2000, pp. 1035-1043
A strategy is presented for modeling of performance variation in polycrysta
lline thin-film transistors (TFT's) due to grain size variation. A Poisson
area scatter is used to model the number of grains in a TFT, which is conve
rted to grain size and substituted into physically based models for thresho
ld and mobility. An increase in device variation is predicted as the device
and grain sizes converge through scaling or process changes. Comparison of
the model with measurements of NMOS TFT's results in reasonable agreement.