Gate oxide reliability is an essential factor in qualifying CMOS technologi
es. An accurate and consistent methodology for determining ultrathin oxide
reliability is therefore needed. In this paper, the crucial steps of this m
ethodology are analysed. First it is demonstrated that soft and hard breakd
own show an identical distribution and therefore extrapolation, from the te
st voltage to a voltage where the soft to hard breakdown prevalence ratio i
s different, is allowed. Secondly, the log-normal distribution is shown to
be inadequate to describe the t(BD)-statistics; only the Weibull distributi
on can be used. Thirdly, based on stress-induced leakage current measuremen
ts, it is concluded that a In(t(BD))-V-g-dependence is well suited to extra
polate high voltage t(BD)-data to low voltage. It is demonstrated that in t
he 1 to 2 V range, the gate voltage shows no threshold value below which th
e oxide degradation is reduced or altered. A detailed analysis in the oxide
thickness range 2 to 5 nm is presented showing that oxide reliability migh
t become a major showstopper fur the further downscaling of CMOS technology
. Possible flaws in the reliability prediction methodology are discussed an
d guidelines for future research are indicated.