Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects

Citation
Ma. Pavanello et al., Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects, SOL ST ELEC, 44(6), 2000, pp. 917-922
Citations number
21
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science","Eletrical & Eletronics Engineeing
Journal title
SOLID-STATE ELECTRONICS
ISSN journal
00381101 → ACNP
Volume
44
Issue
6
Year of publication
2000
Pages
917 - 922
Database
ISI
SICI code
0038-1101(200006)44:6<917:GFDSNF>2.0.ZU;2-5
Abstract
An extended study of the occurrence of inherent parasitic bipolar effects i n conventional and graded-channel fully depleted silicon-on-insulator nMOSF ETs is carried out. The graded-channel device is a new asymmetric channel M OSFET, fabricated through a simple process variation. Measurements and two- dimensional simulations are used to demonstrate that the graded-channel dev ice efficiently alleviates the parasitic BJT action, improving the breakdow n voltage, by the reduction of impact ionization in the high electric field region. Based on process/device simulation and modeling, multiplication fa ctor and parasitic bipolar gain, which are the responsible parameters for t he parasitic BJT action, are investigated separately providing a physical e xplanation. The abnormal subthreshold slope and hysteresis phenomenon are a lso studied and compared. (C) 2000 Elsevier Science Ltd. All rights reserve d.