Conditions of ion implantation into thin amorphous Si gate layers for suppressing threshold voltage shift

Authors
Citation
K. Suzuki et R. Sudo, Conditions of ion implantation into thin amorphous Si gate layers for suppressing threshold voltage shift, SOL ST ELEC, 44(6), 2000, pp. 1043-1047
Citations number
24
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science","Eletrical & Eletronics Engineeing
Journal title
SOLID-STATE ELECTRONICS
ISSN journal
00381101 → ACNP
Volume
44
Issue
6
Year of publication
2000
Pages
1043 - 1047
Database
ISI
SICI code
0038-1101(200006)44:6<1043:COIIIT>2.0.ZU;2-A
Abstract
We collected data of ion-implantation profiles using Monte Carlo simulation , and showed that these profiles can readily be expressed by a joined half Gaussian function. We extracted parameters of the joined half Gaussian func tion from the Monte Carlo data. We also derived a model of the shift in thr eshold voltage caused by the penetration of ion-implanted impurities. Based on the set of profile data. we evaluated the ion-implantation conditions f or As, P, B, and BF2 to suppress the threshold voltage shift. (C) 2000 Else vier Science Ltd. All rights reserved.