Verification of overlap and fringing capacitance models for MOSFETs

Parasitic capacitance and resistance limit the VLSI device performance. Hen ce, a circuit model is needed to treat these effects correctly. This articl e focuses on the circuit models for the overlap capacitance (C-gd.overlap) and the fringing capacitance (C-gd.fringe) of MOSFETs. Comparisons between the models and the device simulations are carried out for verification of t he models. Also, a limitation of C-gd.fringe model for a future device mini aturization is found based on SIA Road Map. We propose a modified C-gd.frin ge model. The effectiveness of the modified model is demonstrated using two circuits. (C) 2000 Elsevier Science Ltd. All rights reserved.