Multiway FPGA partitioning by fully exploiting design hierarchy

In this paper, we present a new integrated synthesis and partitioning metho d for multiple-FPGA applications. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the design hierarch y. We propose a novel multiple-FPGA synthesis and partitioning method which is perfomed in three phases: (1) fine-grained synthesis, (2) functional-ba sed clustering, and (3) hierarchical set-covering partitioning. This method first synthesizes a design specification in a fine-grained way so that fun ctional dusters can be preserved based on the structural nature of the desi gn specification. Then, it applies a hierarchical set-covering partitioning method to form the final FPGA partitions. Experimental results on a number of benchmarks and industrial designs demonstrate that I/O limits are the b ottleneck for CLB utilization when applying a traditional multiple-FPGA syn thesis method on flattened netlists. In contrast, by fully exploiting the d esign structural hierarchy during the multiple-FPGA partitioning, our propo sed method produces fewer FPGA partitions with higher CLB and lower I/O-pin utilizations.