Power-delay optimizations in gate sizing

The problem of power-delay tradeoffs in transistor sizing is examined using a nonlinear optimization formulation. Both the dynamic and the short-circu it power are considered, and a new modeling technique is used to calculate the short-circuit power. The notion of transition density is used, with an enhancement that considers the effect of gate delays on the transition dens ity. When the short-circuit power is neglected, the minimum power circuit i s idential to the minimum area circuit. However, under our more realistic m odels, our experimental results on several circuits show that the minimum p ower circuit is not necessarily the same as the minimum area circuit.