Logical modelling of delay degradation effect in static CMOS gates

A delay model for static CMOS gates with application in gate level logic si mulation is presented. It incorporates the degradation effect on narrow pul ses and is named PID (pure, inertial and degradation). The results lead to the conclusion that the proposed new delay model maintains the high speed o f gate-level logic simulation with a precision comparable to that of electr ical simulation.