A folding ADC preprocessing architecture employing a robust symmetrical number system with gray-code properties

A folding analog-to-digital converter(ADC) preprocessing architecture based on a new robust symmetrical number system (RSNS) is presented. The RSNS pr eprocessing architecture is a modular scheme in which the integer values wi thin each modulus; (comparator states), when considered together, change on e nt a time at the neat position (gray-code properties). Although the obser ved dynamic range of the RSNS ADC is less than the optimum symmetrical numb er system ADC, the RSNS gray-code properties make it particularly attractiv e for error control. With the RSNS preprocessing, the encoding errors due t o comparator thresholds not being crossed simultaneously are eliminated. As a result, the interpolation circuits can be removed and only a small numbe r of comparators are required. Computer generated data is used to help dete rmine the properties of the RSNS. These properties include the dynamic rang e (largest number of distinct consecutive vectors) and the location of the dynamic range within the number system. Closed-form expressions for the dyn amic range are also presented for channel moduli of the form m(1) = 2(k) - 1, m(2) = 2(k), m(3) = 2(k) + 1. RSNS ADC circuit design principles are pre sented. To compare the advantages of the RSNS ADC with previously published results, the transfer function of a 3-channel architecture (k = 2) is eval uated numerically using SPICE.