RT LEVEL TEST SCHEDULING

The paper describes a new model of exploiting parallelism in testing o f VLSI circuits. A circuit at the register transfer level is denoted a s an RTL circuit. The model utilizes the concept of TACG (Test Applica tion Conflict Graph). For the testing process the resource utilization model is defined and used for the TACG construction. Different confli cts that must be taken into account during an RTL circuit test schedul ing are presented. The problem of concurrent test application is trans formed to the one of TACG coloring and covering its nodes. Thus, the g raph theory algorithms call be utilized for an RT level test schedulin g. The way how to use a TACG for an RTL circuit modification is also p resented. The paper offers a methodology that call he utilized during VLSI circuit design process, the final goal of which is to reduce the overall test application time of an RTL circuit.