Design of time delay controller using variable reference model

Reference models are used in many control algorithms to improve transient r esponse characteristics. Most control systems have bounded control inputs t o avoid saturation of the plant. If the reference models do not account for the limits of the control inputs, the control performance of the system ma y deteriorate. In this paper a new approach to avoid saturation is proposed by varying the reference model for time delay control-based systems subjec t to step changes in the reference input. In this scheme, the variable refe rence model is determined based on the information on control inputs and th e size of the step changes in the reference inputs. This scheme was verifie d by application to the BLDC motor position control system in simulations a nd experiments. (C) 2000 Elsevier Science Ltd. Ail rights reserved.