Photoresist patterning and ion implantation degradation effects on flash memory device yield

The undesired effects of photoresist patterning and ion implantation toward achieving optimum yields for flash electrically erasable-programmable read -only memory ((EPROM)-P-2) devices are investigated. The conventional utili zation of a blanket resist with small windows open at the source area of ea ch cell for the conduction of an additional dopant implantation saw a much lower yield similar to 45% for the completed devices when compared to those using isolated resist cell windows for the same implant step similar to 70 %. In addition, the former also displays poorer data retention capability o wing to degraded tunneling dielectric quality, i.e., the device data retent ion loss for blanket resist patterning scheme is similar to 30% lower than what is registered in the improved scheme. The substantial improvement in b oth device yield and data retention capability for the latter arises from t he reduction in the magnitude of surging current, which is made up by the d opant ionized charges, down the substrate via the open windows. (C) 2000 Th e Electrochemical Society. S1099-0062(00)03-013-3. All rights reserved.