Modelling delay and crosstalk in VLSI interconnect for electrical simulation

Authors
Maffezzoni, P Brambilla, A
Citation
P. Maffezzoni et A. Brambilla, Modelling delay and crosstalk in VLSI interconnect for electrical simulation, ELECTR LETT, 36(10), 2000, pp. 862-864
Citations number
2
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
36
Issue
10
Year of publication
2000
Pages
862 - 864
Database
ISI
SICI code
0013-5194(20000511)36:10<862:MDACIV>2.0.ZU;2-4
Abstract
A method for extracting the multi-port equivalent network of a system of m distributed RC lines is presented. The technique enables the time delays an d crosstalk between interconnects to be efficiently analysed by employing c onventional circuit simulators.