CMOS shallow-trench-isolation to 50-nm channel widths

The applicability of shallow-trench-isolation (STI) for CMOS to 50-nm chann el widths has been explored. Transistors with channel width to 50 nm and tr ench width to 200 nm have been fabricated. A comparison of several oxide-fi lled and polysilicon field-plate-filled STI structures is presented includi ng processing, device performance, and isolation leakage, It is shown that V-th roll-off as a function of channel width can be made as small as 65 mV and 145 mV at 100 nm channel width for polysilicon and oxide filled STI, re spectively. Off state currents Less than 5 x 10(-12) A/mu m and subthreshol d slope around 80 mV/dec have been reached. Isolation breakdown voltages ar e about 8 V, poly-filled STI effectively reduces channel edge effects, and provides excellent off-state, on-state, and turn-on characteristics all the way to 50-nm channel widths.