The influence of stud bumping above the MOSFETs on device reliability

Citation
N. Shimoyama et al., The influence of stud bumping above the MOSFETs on device reliability, IEICE T FUN, E83A(5), 2000, pp. 851-856
Citations number
13
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
09168508 → ACNP
Volume
E83A
Issue
5
Year of publication
2000
Pages
851 - 856
Database
ISI
SICI code
0916-8508(200005)E83A:5<851:TIOSBA>2.0.ZU;2-5
Abstract
This paper presents the effect of stress on device degradation in metal-oxi de-semiconductor field-effect transistors (MOSFETs) due to stud bumping. St ud bumping above the MOSFET region generates interface traps at the Si/SiO2 interface and results in the degradation of transconductance in N-channel MOSFETs. The interface traps are apparently eliminated by both nitrogen and hydrogen annealing. However, the hot-carrier immunity after hydrogen annea ling is one order of magnitude stronger than that after nitrogen annealing. This effect is explained by the termination of dangling bonds with hydroge n atoms.