Dynamically variable line-size cache architecture for merged DRAM/Logic LSIs

This paper proposes a novel cache architecture suitable for merged DRAM/log ic LSIs, which is called "dynamically variable line-size cache (D-VLS cache )." The D-VLS cache ran optimize its line-size according to the characteris tic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In o ur evaluation, it is observed that an average memory access time improvemen t achieved by a direct-mapped D-VLS cache is about 20% compared to a conven tional direct-mapped cache with tired 32-byte lines. This performance impro vement is better than that of a doubled-size conventional direct-mapped cac he*.