A high-speed silicon-based few-electron memory with metal-oxide-semiconductor field-effect transistor gain element

The design and operation of a single-electron transistor-controlled memory cell with gain provided by an integrated metal-oxide-semiconductor field-ef fect transistor is described. The field-effect transistor has a split gate, the central section of which is addressed by the single-electron transisto r. This design effectively reduces the size of the cell's memory node such that the memory states are represented by a difference of only a few hundre d electrons, while obtaining output currents in the microamp range. The hys teresis loop in the field-effect transistor current shows clear step discon tinuities which arise from Coulomb oscillations in the single-electron tran sistor's drain-to-source current. The cell operates with write times as sho rt as 10 ns and voltages of less than 5 V at 4.2 K, and operation persists to 45 K. The cell design is compact and the memory is fabricated in silicon -on-insulator material by processes that are compatible with current silico n fabrication methods. (C) 2000 American Institute of Physics. [S0021- 8979 (00)00912-9].