An innovative linear response time-to-digital converter with a branched propagation delay chain

Utilizing the propagation delay in a chain of logic elements to digitize sh ort time intervals has a high potential in various applications because the method has an ultrashort measurement "dead time" and its complete timing c ircuit can be easily integrated in a single semiconductor chip. However, th e existing single-lined chain suffers from serious nonlinearity due to the longer path lengths at the foldings which are unavoidable when the number o f delay elements is large as high time resolution requires. We propose a ne w configuration in which the delay chain is branched. The delay elements of each branch evenly subdivide the corresponding larger folding path so all units have the same delay time. The proposed time-to-digital converter with an 81-delay-unit branched chain and a built-in calibration circuit has bee n implemented on a commercial programmable logic device. It is used to inte rpolate different time durations within the 100 ns period of a standard 10 MHz clock. The digital time deviates less than 0.3 ns throughout the entire range. A similar single-lined delay chain, constructed for comparison, exh ibits timing error up to 32.7 ns. A major improvement in linearity has been achieved by our device. (C) 2000 American Institute of Physics. [S0034-674 8(00)04706-7].