In this paper. for the first time, we demonstrate that incorporation of a s
hallow, lightly doped floating P-layer in the drift region of a high voltag
e CMOS/BiCMOS compatible, 500 V lateral insulated gate bipolar transistor c
an result in a significant improvement of its forward bias safe operating a
rea. Detailed numerical calculations and analysis show that such an approac
h can enhance the on-state voltage handling capability without decreasing t
he breakdown voltage. The position of such a layer is shown to have a signi
ficant impact on the SOA performance of the device for the parameters consi
dered. (C) 2000 Elsevier Science Ltd. All rights reserved.