Evolutionary graph generation system with symbolic verification for arithmetic circuit design

Authors
Homma, N Aoki, T Higuchi, T
Citation
N. Homma et al., Evolutionary graph generation system with symbolic verification for arithmetic circuit design, ELECTR LETT, 36(11), 2000, pp. 937-939
Citations number
6
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
36
Issue
11
Year of publication
2000
Pages
937 - 939
Database
ISI
SICI code
0013-5194(20000525)36:11<937:EGGSWS>2.0.ZU;2-D
Abstract
A novel graph-based evolutionary optimisation technique for arithmetic circ uit synthesis is proposed. Symbolic verification of the generated circuit s tructures is introduced to accelerate the time-consuming evolution process. The evolutionary graph generation (EGG) system based on the proposed techn ique can successfully generate the optimal 16-bit constant-coefficient mult iplier within similar to 2.2h.