A high-density, matched hexagonal transistor structure in standard CMOS technology for high-speed applications

In this paper, a very dense CMOS hexagonal transistor structure is presente d. The main advantages of the transistors are the low parasitic drain and s ource capacitance caused by the small area. The matching properties of this structure have been investigated, and these results have been compared wit h those for traditional finger-style structures. Exploiting the advantages, these transistors are very well suited for high- speed applications with a demand for both good matching and a small area, s uch as multibit current steering D/A converters or wireless applications, T he test chips have been implemented in a standard 0.5-mu m CMOS technology. No adaptations to the standard technology have been made to realize the st ructures.