Linearly-graded surface-doped SOI LDMOSFET with recessed source

A surface-doped SOI (Silicon-On-Insulator) LD (Lateral Double-diffused) MOS FET with a linearly-graded surface-doping profile is proposed which allows low on-resistance and high static and on-state breakdown voltage. The chara cteristics of the proposed LDMOS are verified by the two-dimensional proces s simulator TSUPREM4 and the device simulator, MEDICI. A reduction of the o n-resistance by 83.4% from 62.9 Omega cm to 10.4 Omega cm and an increase i n the static breakdown voltage from 146 V to 205 V and in the on-state brea kdown voltage from 42 V to 96 V for a 10 V gate voltage are obtained for th e proposed device when compared with those of the conventional one. (C) 200 0 Elsevier Science B.V. All rights reserved.