The relentless march of the MOSFET gate oxide thickness to zero

The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3-5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintai ning reliability. Practical limitations due to direct tunneling through the gate oxide may preclude the use of silicon dioxide as the gate dielectric for thicknesses less than 1.3 nm, however. (C) 2000 Elsevier Science Ltd. A ll rights reserved.