A 0.8-MU-M CMOS 2-DIMENSIONAL PROGRAMMABLE MIXED-SIGNAL FOCAL-PLANE ARRAY PROCESSOR WITH ON-CHIP BINARY IMAGING AND INSTRUCTIONS STORAGE

This paper presents a CMOS chip for the parallel acquisition and concu rrent analog processing of two-dimensional (2-D) binary images. Its pr ocessing function is determined by a reduced set of 19 analog coeffici ents whose values are programmable with 7-b accuracy. The internal pro gramming signals are analog, but the external control interface is ful ly digital. On-chip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feed back to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels o ut the nonlinear dependence of the analog circuitry with the programmi ng signal and reduces the influence of interchip technological paramet ers random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the c ell array and four 2-D binary images spatially distributed over the pr ocessing array. It also includes the necessary control circuitry to re alize the stored instructions in any order and also to realize program mable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-mu m single-poly double-metal technology and features 2-mu s operation speed (time required to process an image ) and around 7-b accuracy in the analog processing operations.