A 32-B RISC DSP MICROPROCESSOR WITH REDUCED COMPLEXITY/

This paper presents a new 32-b reduced instruction set computer/digita l signal processor (RISC/DSP) architecture which can be used as a gene ral purpose microprocessor and in parallel as a 16-/32-b fixed-point D SP. This has been achieved by using RISC design principles for the imp lementation of DSP functionality. A DSP unit operates in parallel to a n arithmetic logic unit (ALU)/barrelshifter on the same register set. This architecture provides the fast loop processing, high data through put, and deterministic program flow absolutely necessary in DSP applic ations. Besides offering a basis for general purpose and DSP processin g, the RISC philosophy offers a higher degree of flexibility for the i mplementation of DSP algorithms and achieves higher clock frequencies compared to conventional DSP architectures. The integrated DSP unit pr ovides instruction set support for highly specialized DSP algorithms. Subword processing optimized for DSP algorithms has been implemented t o provide maximum performance for 16-b data types. While creating a un ified base for both application areas, we also minimized transistor co unt and ne reduced complexity by using a short instruction pipeline. A parallelism concept based on a varying number of instruction latency cycles made superscalar instruction execution superfluous.