LOW-POWER LOGIC STYLES - CMOS VERSUS PASS-TRANSISTOR LOGIC

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more pow er-efficient than complementary CMOS. However, new comparisons perform ed on more efficient CMOS circuit realizations and a wider range of di fferent logic cells, as well as the use of realistic circuit arrangeme nts demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implem ented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to vo ltage scaling and transistor sizing, as well as generality and ease-of -use, are additional advantages of CMOS logic gates, especially when c ell-based design and logic synthesis are targeted. This paper shows th at complementary CMOS is the logic style of choice for the implementat ion of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.