In this paper, we propose a chip architecture and design techniques to simu
ltaneously reduce both the chip cost and power consumption of system-on-a-c
hip (SOCs). The chip cost of SOCs consists of the design cost, the mask cos
t, the fabrication cost, the package cost, and the test cost. In case that
the production volume of one design is large, the fabrication cost becomes
relatively larger than other costs. The minimization of the fabrication cos
t by shrinking the chip area has been the main problem to reduce the chip c
ost. SOCs are not always mass-produced and their design and the mask costs
are dominant. We need new design criteria and a new design methodology for
SOCs whose production volume is small. Our major contribution is a proposal
of a design methodology based on new criteria suitable for SOC design. In
our methodology, system designers use a pre-fabricated chip, called Flexibl
e System LSI (FlexSys) chip, which consists of a processor, memories, and o
ther cores specific to an application domain. At the fabrication phase, the
power supply for unused parts of the FlexSys chip is cut off using a few a
dditional masks which are designed for a specific application. This leads t
he reduction of wasteful power consumed by circuits which do not essentiall
y contribute to the computation of the application. Since the basic die of
the FlexSys is fabricated as a general purpose product, we can reduce the c
ost of the dies drastically. Experimental results show that about 30% power
reduction can be achieved without performance loss by reducing the wastefu
l power consumption.